As a Design Verification Engineer you will contribute to the functional verification of LPDDR4/5 memory controllers. This is a hands on role, driving next generation product development with a high level of contribution and knowledge base needs. Key responsibilities include: • Support unit and super-unit debug on simulation platforms.

• Develop test plans, test benches and tests, creating sequencers, drivers, checkers, and monitors in a UVM environment. • Enhance test benches and tests to achieve coverage goals. • Create and support test environments for different design hierarchy levels.

• Learn the architecture and micro architecture by studying specifications and direct interaction with architects and logic designers.

Minimum requirements: • BSEE, Computer Engineer or comparable and 2+ years of experience • Experienced with verification methodology such as UVM/VMM/OVM. • ARM-ACE Coherency or LPDDR4/5 experience would be a bonus. • Composed functional coverage assertions, preferably using System Verilog. Preferred candidate will possess the following: • Exposure to either CPU coherency protocols or DDR memory controllers. • Proficient in System Verilog, C++, and Python/Perl scripting • Excellent verbal and written communication skills. • Developed test plans of complex systems containing multiple state machines and protocol rules.