Location:
Remote
Duration
: 12 months
Role Mandate:
The team is responsible for doing digital design for graphics IP and is looking for an individual to collaborate on IP integration and quality checks with some limited RTL coding.
Candidate Value Proposition:
The ideal candidate will collaborate with a team of designers to assist with graphics IP development by doing top-level integration work.
Role Responsibilities (including, but not limited to):
• Perform IP integration
• Ensure integrated IP meets quality checks like VC Static Lint/CDC/RDC/DFT.
• Python scripting
• TCL scripting
• Run RTL release flows (shell scripts, automated quality checks)
• Filelist maintenance
• Support hand-off and integration of blocks into larger SOC environments
• Test debug
• Dashboard maintenance
Performance Measurement:
Performance is measured based on meeting deadlines by delivering on time while meeting code quality metrics and DV quality metrics.
Must Have Skills:
• 4+ years of experience as a Digital Design Engineer or IP Integration Engineer.
• Experience in RTL coding and coding for low power in ASICs.
• Familiarity with Verilog and SystemVerilog coding
• Perl, Tcl and Python (or similar) scripting experience
• Familiarity with Synopsys toolset.
• General silicon debug skills
Nice-to-Have Skills:
• MSEE/CS or equivalent experience
• Recent track record of projects where the individual performed IP integration that were successfully taped out.
• Knowledge of standard interfaces (AXI/APB/OCP)
Soft Skills:
• Strong verbal and written communication skills
Educational Requirements:
• BS Electrical Engineering/Computer Science/Computer Engineering or equivalent experience
Interview Process:
• 2 Rounds, 45 mins – 1 hour
• Coding exercises
Silicon DD Engineer III
Silicon DD Engineer III
Contract Type:
Contract
Specialization:
ASIC Flow
Sub-Specialty:
RTL Design (Register Transfer Level)
Date Published:
22-Feb-2025
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