Silicon Design Engineer 5

• Purpose of the Team: The purpose of this team is to create custom silicon IP for Microsoft products.
• Key projects: Next Gen XBOX IP design
• Typical task breakdown and operating rhythm: The role will consist of 20% meetings and 80% coding.

Compelling Story & Candidate Value Proposition
What makes this role interesting? - Opportunity to work on cutting edge technology for next generation XBOX products.

Candidate Requirements

• Years of Experience Required: 10+ years of experience in hardware design
• Degrees or certifications required: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related degree required to be eligible for this role.
• Disqualifiers: Candidates with constant job hopping (need to be able to stick out the contract), lack of recent experience with sub-system integration or fabric generation with 3rd party tooling will not be eligible for the role.
• Best vs. Average: The ideal resume would demonstrate the ability to pick up and own legacy RTL. Quickly ramp up on previous functionality and be able to debug related test issues. Able to review and fix static checks including CDC, RDC, and lint. Ability to look at static timing reports and implement solutions to any timing issues.
• Performance Indicators: Performance will be assessed based on meeting deadlines with pre-defined quality metrics.

Top 3 Hard Skills Required + Years of Experience
1. Minimum 3+ years of Strong design knowledge of industry standard bus interfaces such as AMBA AXI protocol.
2. Minimum 3+ years static timing analysis
3. Minimum 7+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Static Checking closure (CDC/RDC/LINT).

Hard Skills Assessments

• Expected Dates that Hard Skills Assessments will be scheduled: after
• Hard Skills Assessment Process: The assessment process will include 1 round of assessment.
• Required Candidate Preparation: Candidates should be prepared to discuss previous relevant project/design experience and be prepared to answer technical questions w.r.t. related skills.

Job Description

Summary:
Front-End Silicon Design Engineer who is responsible for front end design tasks at the block and sub-system levels. These tasks include RTL design, sub-system integration, RTL generation via 3rd party tools, and repository management as well as debug of ported legacy code into a new design environment.

Job Responsibilities:

• Responsible for various integration tasks at the block level
• Responsible for various integration tasks at the sub-system level
• Manage repos for shared collateral across design teams
• Review and waive CDC/RDC/Lint issues
• Review static timing violations
• Debug and fix verification issues

Skills:

• Knowledge of the RISC-V architecture
• Strong design knowledge of the industry standard bus interfaces such as AMBA AXI protocol
• Worked with leading-edge technologies e.g. 5 nm or smaller.
• Knowledge of GIT repositories
• Scripting python, perl, tcl, etc.
• SystemVerilog and Verilog

Education/Experience:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related degree required.
• 10+ years of experience in hardware design
• 7+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/LINT closure

• Purpose of the Team: The purpose of this team is to create custom silicon IP for Microsoft products.
• Key projects: Next Gen XBOX IP design
• Typical task breakdown and operating rhythm: The role will consist of 20% meetings and 80% coding.

Compelling Story & Candidate Value Proposition
What makes this role interesting? - Opportunity to work on cutting edge technology for next generation XBOX products.

Candidate Requirements

• Years of Experience Required: 10+ years of experience in hardware design
• Degrees or certifications required: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related degree required to be eligible for this role.
• Disqualifiers: Candidates with constant job hopping (need to be able to stick out the contract), lack of recent experience with sub-system integration or fabric generation with 3rd party tooling will not be eligible for the role.
• Best vs. Average: The ideal resume would demonstrate the ability to pick up and own legacy RTL. Quickly ramp up on previous functionality and be able to debug related test issues. Able to review and fix static checks including CDC, RDC, and lint. Ability to look at static timing reports and implement solutions to any timing issues.
• Performance Indicators: Performance will be assessed based on meeting deadlines with pre-defined quality metrics.

Top 3 Hard Skills Required + Years of Experience
1. Minimum 3+ years of Strong design knowledge of industry standard bus interfaces such as AMBA AXI protocol.
2. Minimum 3+ years static timing analysis
3. Minimum 7+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Static Checking closure (CDC/RDC/LINT).

Hard Skills Assessments

• Expected Dates that Hard Skills Assessments will be scheduled: after
• Hard Skills Assessment Process: The assessment process will include 1 round of assessment.
• Required Candidate Preparation: Candidates should be prepared to discuss previous relevant project/design experience and be prepared to answer technical questions w.r.t. related skills.

Job Description

Summary:
Front-End Silicon Design Engineer who is responsible for front end design tasks at the block and sub-system levels. These tasks include RTL design, sub-system integration, RTL generation via 3rd party tools, and repository management as well as debug of ported legacy code into a new design environment.

Job Responsibilities:

• Responsible for various integration tasks at the block level
• Responsible for various integration tasks at the sub-system level
• Manage repos for shared collateral across design teams
• Review and waive CDC/RDC/Lint issues
• Review static timing violations
• Debug and fix verification issues

Skills:

• Knowledge of the RISC-V architecture
• Strong design knowledge of the industry standard bus interfaces such as AMBA AXI protocol
• Worked with leading-edge technologies e.g. 5 nm or smaller.
• Knowledge of GIT repositories
• Scripting python, perl, tcl, etc.
• SystemVerilog and Verilog

Education/Experience:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related degree required.
• 10+ years of experience in hardware design
• 7+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/LINT closure