Physical Design
INDUSTRY: SEMICONDUCTOR
Common Essential Duties & Responsibilities:
• Drive standard P&R tools and perform timing/power analysis and optimization to meet timing/power/area targets.
• Support sign-off tasks, including block level timing/power/area closure, power integrity, signal integrity and physical sign-off flow.
• Solid understanding of the CPU design/integration flow with extensive experience in taping out designs.
• Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure.
• Scripting Python, TCL, Shell, and other script languages.
Requirements:
• BSEE or MSEE with 5+ years relevant experience.
• Ability to work in a cross functional team environment and to balance innovation and execution. Includes investigation of new tools and design techniques.
• Enjoys working in a collaborative work environment, sharing ideas, and learning from others.
• Hands-on experience with Synopsys ICC2 and Mentor physical verification tools are a plus.
