Analog & Mixed-Signal Design
Custom Analog IC and Mixed-Signal Designers
Analog and mixed-signal design is highly subspecialized. We match the specific IP block, process node, and PDK to the right engineer. So every analog submission is tuned to your circuit, not just your discipline.
What they do
Subspecialty-Matched Analog Engineering from Schematic Through Silicon
Analog engineers at Game 7 are matched to the specific IP block they'll design. PLL, VCO, ADC, DAC, LDO, AFE, or RF front end. A PLL designer for a high-speed SerDes PHY is solving fundamentally different problems than an AFE designer for an automotive radar front end or a data-converter designer for a coherent optical transceiver.
We ask about the IP block, the process node, the PDK, and the performance targets before matching. Because placing a VCO designer on a delta-sigma ADC program helps no one. Subspecialty fit is the starting point.
Scope of work
- PLL, VCO, and frequency synthesis design and silicon characterization
- High-speed ADC and DAC design (pipeline, SAR, and delta-sigma architectures)
- LDO, bandgap reference, and on-chip power management circuit design
- Analog layout in Cadence Virtuoso. Custom cell placement, matching, and shielding
- SPICE simulation across PVT corners (Spectre, HSPICE, Monte Carlo analysis)
- Mixed-signal verification: Verilog-AMS testbench development and AMS co-simulation
- RF front-end design: LNA, mixer, VCO, and PA for wireless and radar applications
- Silicon bring-up and lab characterization of analog IP (oscilloscope, VNA, spectrum analyzer)
Tools & Technologies
The stack our Analog & Mixed-Signal engineers actually ship in.
Program context
Subspecialty Matched to Program Requirement
Analog and mixed-signal design is highly subspecialized. A PLL designer for a high-speed SerDes PHY is solving fundamentally different problems than an AFE designer for an automotive radar front end or a data converter designer for a coherent optical transceiver. Each requires a different toolkit, different simulation methodology, and different silicon intuition. Game 7 treats every analog subspecialty as its own staffing profile. We ask about the specific IP block, the process node, the PDK, and the performance targets before matching.
FAQ
Common Questions on Analog & Mixed-Signal Design Staffing
Why is analog design talent so difficult to find?+
Analog design cannot be automated the way digital design can. There is no synthesis tool for an LDO or a PLL. Every transistor is hand-sized, hand-biased, and hand-placed. The skill accumulates over decades. Engineers who have silicon-proven designs at advanced nodes (16nm, 7nm, 5nm) with FinFET-specific analog techniques are extremely rare. The pipeline of new analog designers is thin because most EE programs have shifted toward digital, software, and machine learning.
What's the difference between an analog design engineer and an analog layout engineer?+
An analog design engineer works at the schematic level. Sizing transistors, setting bias points, designing circuit topologies, and running SPICE simulations across PVT corners. An analog layout engineer takes the schematic and physically implements it in silicon: placing devices, drawing shapes, handling parasitic-sensitive matching and shielding. Top analog teams have both, and the best outcomes come when the layout engineer is involved in the design phase. Not handed a finished schematic as a spec. We staff both profiles.
Can Game 7 place SerDes analog designers specifically?+
Yes. SerDes analog design. PLLs, CDRs, transmitter drivers, and receiver AFEs for high-speed serial links (PCIe, USB, Ethernet, custom interfaces). Is one of the highest-demand analog subspecialties in semiconductor. We have a dedicated page for SerDes Design Engineers and treat this as a separate staffing profile from general analog. Tell us the interface standard, the data rate, and the process node.
What process nodes do your analog engineers have experience with?+
Our analog engineers have designed at planar nodes (180nm through 28nm) as well as FinFET nodes (16nm, 12nm, 7nm, 5nm). For FinFET analog work, we specifically ask about experience with quantized device widths, reduced intrinsic gain, and layout-dependent effects (LDE) that make FinFET analog behavior different from planar. Placing an engineer whose only analog experience is 180nm on a 7nm program is a mismatch we avoid.
Related disciplines
Cross-Links Across the Team
High-Speed SerDes Designers, 28G Through 112G PAM4
High-speed serial link specialists for PHY-layer analog.
Physical Design Engineers →Floorplan, P&R, STA, and Signoff Engineers for Advanced Process Nodes
Analog-aware back-end engineers for mixed-signal SoC integration.
Design Verification Engineers →UVM Architects and DV Leads with Verification Closure Experience
AMS verification engineers for analog/digital co-simulation.
Let's talk
Need an Analog & Mixed-Signal Engineer?
Tell us the program. We'll send a shortlist of 2-4 qualified engineers within days.