Section
About the Role
Title: DFT Architect
Headcount: 1
Location: Austin, Texas (Remote approved)
Contract: 6-month minimum; Start: July 2026
Interview Process: 2 Teams Interviews
Feedback SLA: Weekly sync (Fridays at 11:30 AM Central).
Why Hiring:
- Critical need for DFT expertise to support internal SoC project following the departure of previous support resources.
- Current team lacks internal capacity to handle DFT implementation without significant project schedule delays.
End Product:
- Radiation-hardened System on a Chip (SoC) featuring an ARM Cortex M series CPU, integrated analog components, and various peripherals.
Tech/Domain Environment:
- Cadence DFT tools (Primary preference)
- Perl and Python programming
- JTAG, Scan, and Memory BIST
Job Duties (6-10 bullets):
- Architect DFT implementation for MCU-based SoC.
- Perform netlist-level scan chain insertion.
- Generate test patterns for DFT modes.
- Run simulations to verify coverage and DFT feature functionality.
- Integrate JTAG for post-silicon testing requirements.
- Support post-silicon validation and troubleshooting (approx. 10-20% of role).
- Document DFT architecture and implemented test features.
- Collaborate with logic design, verification, and physical design teams.
Must Haves (hard gates; 6-12 bullets, all testable/quantified):
- 10+ years of professional experience in DFT architecture, implementation, and verification.
- Proven experience generating test patterns for DFT modes in a production environment.
- Proficiency in Perl and Python programming for automation in production.
- US-based residency due to export requirements.
- Demonstrated ability to perform scan chain insertion and coverage simulation.
Nice to Haves (5-10 bullets):
- Experience with analog and digital peripheral testing.
- Familiarity with Cadence DFT tool suite.
- Experience with radiation-hardened design requirements.
- Prior experience supporting post-silicon bring-up and pattern debugging.
Disqualifiers (3-6 bullets):
- Less than 10 years of professional DFT experience.
- Only academic or Proof of Concept (POC) experience in DFT.
- Inability to work within US export compliance requirements.