How to Hire a DFT Engineer (and Tell an Architect From an Operator)

DFT decides your per-unit test cost before floorplan. How to hire a scan/ATPG engineer or a true DFT architect, and tell the difference on a resume.
Design-for-test is the discipline most often treated as a downstream checkbox and most punishing when you hire it wrong. The decisions a DFT engineer makes, often before floorplan, set the per-unit cost of testing every chip you ship. A mis-hire here does not show up in a design review. It shows up months later as a test-time bill at the OSAT that nobody budgeted for.
Why a DFT Mis-Hire Costs You at Volume
Test time is money. On the automatic test equipment that screens every die, you are billed for the seconds each part spends in the socket, and the scan architecture and compression strategy that determine those seconds are set early in the design. If the engineer who owns DFT cannot architect for test cost, you pay the difference on every unit, forever.
Operator vs. Architect: The Distinction That Matters
An operator executes a flow: insert scan, run ATPG, hit a coverage target on a block. An architect defines the test strategy for the whole chip, including scan-chain architecture, compression ratio, memory BIST planning across hundreds of SRAMs, and the test-time budget against the production ATE platform. Both are valid hires, but they are not interchangeable, and the rate difference reflects the responsibility difference.
The Skills That Map to Real Test Cost
The credible toolchain is specific: scan insertion and compression with Synopsys DFTMAX, Cadence Modus, or Siemens Tessent; ATPG with Synopsys TetraMAX; memory BIST; and a working understanding of the production test platform, whether that is Teradyne's UltraFLEX or the Advantest V93000. An architect can connect those choices to test time and yield, not just run them to a coverage number.
The Automotive Wrinkle
Automotive has reshaped DFT demand. ISO 26262 functional safety, at ASIL-B and ASIL-D, requires in-field fault detection, which means Logic BIST architectures that run diagnostics while the vehicle is operating or between ignition cycles. That is a different problem than production scan test, and engineers who can architect an LBIST scheme against a formal safety case are genuinely scarce.
The Rarest Hire: The Design-Plus-Production Bridge
The DFT engineer who is hardest to replace bridges two worlds that usually do not talk: the design side (scan architecture, ATPG, coverage closure) and the production side (ATE program bring-up, yield correlation at the OSAT, debugging test escapes that only appear in silicon). Most DFT engineers are deep on one side. The architect who has lived on both can make tradeoffs that touch wafer cost directly, and that is a meaningfully harder search.
When to Start the Search
Game 7 places senior and principal DFT engineers and architects who have done this across multiple tape-outs.
Because the architecture is best locked before floorplan, the time to hire a DFT architect is during early planning, not at netlist handoff. If DFT ownership on your program is unclear and you are approaching floorplan, that is the conversation worth having now.
FAQ
Frequently Asked Questions
What's the difference between a DFT engineer and a DFT architect?
A DFT engineer executes scan, ATPG, and BIST insertion against a defined plan. A DFT architect defines the test strategy, including scan architecture, compression ratio, memory BIST plan, and ATE test-time budget, the decisions that set per-unit test cost at volume.
When should I hire a DFT architect?
Before floorplan. Scan-chain count, compression ratio, and BIST strategy need to be locked early; changing them after netlist handoff carries multi-week remediation cost and lowers the compression you can achieve.
What automotive DFT experience should I require?
ISO 26262 ASIL-B and ASIL-D Logic BIST experience, the in-field, in-system fault detection that safety-critical automotive chips require, which is a different problem than production scan test.
Which DFT tools should a strong candidate know?
Synopsys DFTMAX and TetraMAX, Cadence Modus, or Siemens Tessent for insertion, compression, and ATPG, plus memory BIST and familiarity with ATE platforms such as the Teradyne UltraFLEX and Advantest V93000.
Written by
Game 7 Staff
